Stacking die package structure for semiconductor devices and method of the same
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United States of America Patent
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Issued Date -
May 21, 2009
app pub date -
Nov 21, 2007
filing date -
Nov 21, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.
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