METHOD FOR FORMING A VIA IN A SUBSTRATE AND SUBSTRATE WITH A VIA

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United States of America Patent

APP PUB NO 20090140436A1
SERIAL NO

12241219

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED SEMICONDUCTOR ENGINEERING INC26 CHIN 3RD ROAD NANZIH DIST KAOHSIUNG 811

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wang, Meng-Jen Kaohsiung , TW 74 713

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