Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
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Oct 26, 2010
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app pub date -
Feb 10, 2009
filing date -
Dec 9, 1996
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Abstract
A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
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Patent Owner(s)
- PACT XPP TECHNOLOGIES AG
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Münch, Robert | Uhlandstrasse 30 | 10 | 153 |
Vorbach, Martin | Gotthardstrasse 117a | 174 | 5376 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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