Importance

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Abstract

Methodologies and structures are disclosed for providing multilayer electronic devices having low inductance and high ratings, such as for capacitor devices for uses involving faster pulsing and higher currents. Plural layer devices are constructed for relatively lowered inductance by relatively altering typical orientation of capacitors such that their electrodes are placed into a vertical position relative to an associated circuit board. Optionally, individual leads may be formed so that the resulting structure can be used as an array. Internal electrodes may be arranged for reducing current loops for associated circuits on a circuit board, to correspondingly reduce the associated inductance of the circuit board mounted device. Leads associated with such devices may have added tab-like structures which serve to more precisely place the lead, to improve the lead to capacitor strength, and to promote lower resistance and inductance. Disclosed designs for reducing associated inductance may be practiced in conjunction with various electric devices, including capacitors, resistors, inductors, or varistors.

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First Claim