BALANCED PROGRAMMING RATE FOR MEMORY CELLS
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United States of America Patent
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Issued Date -
Jun 11, 2009
app pub date -
Oct 24, 2007
filing date -
Oct 24, 2007
priority date (Note) -
Abandoned
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Abstract
A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the LSS may also be shifted, according to an incremental shift number (which may be the PBE-counter). The ED bits of the shift-niumber inherently have an evenly balanced distribution The ED bits of the PBE-counter inherently have an evenly balanced distribution.
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