INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME

Number of patents in Portfolio can not be more than 2000

United States of America Patent

SERIAL NO

11965157

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating base adhered on the active surface of the die by adhesion glue; a through silicon via (TSV) open from the back side of the die to expose the bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via; solder balls melted on terminal pads, wherein the terminal pads located on the core and/or the die.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
ADVANCED CHIP ENGINEERING TECHNOLOGY INCNO 65 GUANGFU N RD HUKOU TOWNSHIP HSINCHU COUNTY 303 R O C

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Jui-Hsien Jhudong Township , TW 39 576
Lee, Chi-Chen Taipei City , TW 51 949
Tsai, Mon-Chin Chung-tong Town , TW 11 137
Yang, Wen-Kun Hsin-chu City , TW 109 2809

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation