Programmable logic based latches and shift registers
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United States of America Patent
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Aug 11, 2009
Grant Date -
Jul 2, 2009
app pub date -
May 12, 2008
filing date -
Dec 26, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.
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