STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER

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United States of America Patent

APP PUB NO 20090173967A1
SERIAL NO

11969618

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Abstract

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This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer. This invention also provides a twist-bonded semiconductor layer on a polycrystalline base layer, as well as methods for fabricating the aforementioned FETs.

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GLOBALFOUNDRIES INCMAPLES CORPORATE SERVICES LIMITED PO BOX 309 UGLAND HOUSE GRAND CAYMAN KY1-1104

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hamaguchi, Masafumi White Plains , US 15 72
Hasumi, Ryoji Crompond , US 13 96
Saenger, Katherine L Ossining , US 127 2993
Yin, Haizhou Poughkeepsie , US 244 3095

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