Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System

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United States of America Patent

SERIAL NO

12418550

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A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.

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Patent Owner(s)

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SUPER TALENT ELECTRONICS INC2079 N CAPITOL AVE SAN JOSE CA 95132

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Charles C Cupertino , US 133 8384
Ma, Abraham C Fremont , US 154 8758
Shin, Myeongjin San Ramon , US 4 558
Yu, Frank Palo Alto , US 62 5303

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