METHOD AND SYSTEM FOR IMPROVING ELECTRICAL PERFORMANCE OF VIAS FOR HIGH DATA RATE TRANSMISSION
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United States of America Patent
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N/A
Issued Date -
Aug 13, 2009
app pub date -
Feb 9, 2009
filing date -
Feb 8, 2008
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A method and system for reducing via hole parasitic effects on PCB transmission channels. In order to reduce the effects of excess via capacitance in PCB structures, PCB via modeling accuracy for high speed serial data transmissions is improved by utilizing lower permittivity reinforcement and z-axis conducting methods. A method to accomplish this includes creating a channel within the circuit board to accommodate a via hole, filling the created channel with a predetermined amount of dielectric material, forming the via hole, and electrically coupling the top layer of the structure to at least an inner signal substrate layer of the structure.
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