OFF-CHIP ACCESS WORKLOAD CHARACTERIZATION METHODOLOGY FOR OPTIMIZING COMPUTING EFFICIENCY
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United States of America Patent
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Issued Date -
Aug 20, 2009
app pub date -
Feb 17, 2009
filing date -
Feb 14, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system, apparatus, and method are provided which allows for reducing power consumption in dynamic voltage and frequency scaled processors while maintaining performance within specified limits. The method includes determining the off-chip stall cycle in a processor for a specified interval in order to characterize a frequency independent application workload in the processor. This current application workload is then used to predict the application workload in the next interval which is in turn used, in conjunction with a specified performance bound, to compute and schedule a desired frequency and voltage to minimize energy consumption within the performance bound. The apparatus combines the aforementioned method within a larger-scale context that reduces the energy consumption of any given computing system that exports a dynamic voltage and frequency scaling interface. The combination of the apparatus and method form the overall system.
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