Semiconductor interconnect structure with stacked vias separated by signal line and method therefor

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United States of America Patent

PATENT NO 9466577
APP PUB NO 20090212441A1
SERIAL NO

12035843

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Abstract

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A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming a first via in the first passivation layer to expose the first conductive layer, forming a second conductive layer over the first passivation layer and within the first via to electrically connect to the first conductive layer, forming a second passivation layer over the second conductive layer, and forming a second via in the second passivation layer to expose the second conductive layer. The second via is smaller than the first via. The second via is either physically separate from or disposed over the first via. The second conductive layer within the second via has a flat surface which is wider than the second via. An under bump metallization is formed in the second via and electrically connected to the second conductive layer.

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Patent Owner(s)

  • STATS CHIPPAC PTE. LTE.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Yaojian Singapore, SG 330 9780

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