CONTROLLED EDGE RESISTIVITY IN A SILICON WAFER
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United States of America Patent
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Issued Date -
Aug 27, 2009
app pub date -
Dec 23, 2008
filing date -
Feb 26, 2008
priority date (Note) -
Abandoned
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Abstract
An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer.
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