Serial Buffer To Support Reliable Connection Between Rapid I/O End-Point And FPGA Lite-Weight Protocols
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United States of America Patent
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Issued Date -
Sep 10, 2009
app pub date -
Mar 6, 2008
filing date -
Mar 6, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A serial buffer includes a first port configured to implement an serial rapid I/O (sRIO) protocol and a second port configured to implement a Lite-weight serial (Lite) protocol. SRIO packets received on the first port are translated into Lite request packets compatible with the Lite protocol. The Lite request packets are transmitted to the second port. Lite response packets compatible with the Lite protocol are returned to the second port in response to the Lite request packets. The Lite response packets are translated into sRIO response packets compatible with the sRIO protocol. These sRIO response packets are returned to the first port, thereby providing a mechanism to acknowledge successful transmissions from the first port to the second port. Unsuccessful transmissions are identified by a timeout mechanism. The serial buffer also enables transfers from the second port to the first port in a similar manner.
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