Energy efficient processing device
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United States of America Patent
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Issued Date -
Sep 10, 2009
app pub date -
May 22, 2007
filing date -
May 22, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A network processor with a high performance in computing throughput, size and power density for use in applications such as Software Defined Radio (SDR) mesh topology. The network processor uses a core architecture comprised of a programmable microcoded sequencer to implement state management and control, a data manipulation subsystem controlled by fully decoded microinstructions. To save power, the core architecture employs a fully decoded microcoded control unit, multiplexer based register select/write logic, between 10000 to 20000 gates, a power consumption of less than 10 mW.
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