Importance

Loading Importance Indicators...

Abstract

Clock signals used to operate core receive logic and core transmit logic within a serial buffer are dynamically enabled and disabled to minimize power consumption. A physical layer interface and an event monitor are continuously enabled to identify the start of incoming transactions. Upon detecting the start of an incoming transaction, the event monitor activates a packet retry signal, and also initiates generation of a receive clock signal within the serial buffer. By the time that the incoming transaction is re-sent, the receive clock signal is enabled, thereby enabling the associated core receive logic. Once enabled, the receive clock signal remains enabled until the period between consecutive incoming transactions exceeds a timeout period, whereupon the receive clock signal is disabled. A similar mechanism is provided to dynamically enable and disable a transmit clock signal, which enables and disables corresponding core transmit logic of the serial buffer.

Loading the Abstract Image...

First Claim