US Patent Application No: 2009/0231,904

FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS

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Sep 17, 2009
Publication date
May 22, 2009
filing date
12/471,059
serial no
Granted
status

ALSO PUBLISHED AS: 8077494

Importance

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Abstract

A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.

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First Claim

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Patent Owner(s)

Patent Owner	Address	Total Patents
PATRENELLA CAPITAL LTD., LLC	WILMINGTON, DE	103

International Classification(s)

G11C:STATIC STORES

[Classification Symbol]

[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Miyamoto, Hideaki	Ogaki, JP	54	94

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