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Abstract

Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.

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First Claim