Seed Layers for Electroplated Interconnects

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United States of America Patent

SERIAL NO

12471557

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Abstract

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One embodiment of the present invention is a method for depositing two or more seed layers for electroplating metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing a continuous seed layer over the sidewalls and bottom of the at least one opening using a first set of deposition parameters; and (b) depositing a second seed layer over the continuous seed layer using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) the continuous and second seed layers being sufficiently thick over the field to enable uniform electroplating across the substrate, and (iii) after depositing the seed layers, there is sufficient room for electroplating inside the at least one opening.

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Patent Owner(s)

Patent OwnerAddress
COHEN URI DR4147 DAKE AVENUE PALO ALTO CA 94306

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cohen, Uri Palo Alto, US 56 1249

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