Test pads coupled with leads unconnected with die pads
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United States of America Patent
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Jun 7, 2011
Issued Date -
N/A
app pub date -
Jun 30, 2009
filing date -
Jan 19, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
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