Package-Borne Selective Enablement Stacking
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United States of America Patent
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app pub date -
May 7, 2009
filing date -
Apr 3, 2007
priority date (Note) -
Abandoned
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Abstract
The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs.
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