Semiconductor package device, semiconductor package structure, and fabrication methods thereof
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United States of America Patent
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Nov 6, 2012
Grant Date -
Dec 3, 2009
app pub date -
Dec 4, 2008
filing date -
May 28, 2008
priority date (Note) -
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Abstract
A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
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