USE OF STATE NODES FOR EFFICIENT SIMULATION OF LARGE DIGITAL CIRCUITS AT THE TRANSISTOR LEVEL
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United States of America Patent
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app pub date -
Jun 12, 2009
filing date -
Aug 8, 2005
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Abandoned
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Abstract
A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state.
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