Method and Apparatus for On-Chip Testing of High Speed Frequency Dividers
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United States of America Patent
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Issued Date -
Dec 31, 2009
app pub date -
Jun 27, 2008
filing date -
Jun 27, 2008
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Abstract
Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.
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