ON-DIE THEVENIN TERMINATION FOR HIGH SPEED I/O INTERFACE
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United States of America Patent
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N/A
Issued Date -
Jan 14, 2010
app pub date -
Jul 14, 2008
filing date -
Jul 14, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The method, system, and apparatus of on-die Thevenin termination for high speed I/O interface are disclosed. In one embodiment, a system of terminating a transmission line of a chip includes a pull-up circuit located within the chip comprising a voltage source and a positive switch device coupled with the transmission line of the chip, a pull-down circuit located within the chip comprising a ground and a negative switch device coupled with the transmission line of the chip, a resistor located within the chip coupled with the voltage source, the positive switch device, the ground, the negative switch device, and a pad coupled with the resistor to terminate the transmission line of the chip. The system may include resistors coupled in parallel with each other. The system may include an impedance module to determine a load impedance value as seen from the pad that matches a source impedance value.
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