Delay line circuit for generating a fixed delay
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United States of America Patent
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Issued Date -
Jan 14, 2010
app pub date -
Jul 11, 2008
filing date -
Jul 11, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit.
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