LOGIC OUTPUT STAGE OF INTEGRATED CIRCUIT PROTECTED AGAINST BATTERY INVERSION

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20100014201A1
SERIAL NO

12447835

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The invention relates to integrated electronic circuits in MOS technology that have to be supplied by a cell or a battery that have a relatively high voltage capable of destroying the circuit in the event of a battery connection error, most particularly when a negative voltage is connected to an output of the integrated circuit. The logic output stage connected to this output comprises two pMOS transistors in series operating in push-pull mode under the control of the logic input signal, a first transistor being connected to a high supply terminal of the integrated circuit and the second transistor to a low supply terminal; the output is taken at the junction point of the two transistors. A conduction control circuit, capable of applying a negative voltage relative to the low supply terminal to the gate of the second transistor when the logic input signal passes to a level tending to turn off the first transistor, is interposed between the input and the gate of the second transistor.

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Patent Owner(s)

Patent OwnerAddress
E2V SEMICONDUCTORSFRENCH SHENGAIGELEIFU

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Coquille, Pierre Theoffrey, FR 2 13
Masson, Thierry Varces, FR 14 115

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