Method For Preparing Multi-Level Flash Memory Structure
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United States of America Patent
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Issued Date -
Feb 18, 2010
app pub date -
Aug 12, 2008
filing date -
Aug 12, 2008
priority date (Note) -
Abandoned
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Abstract
A method for preparing a multi-level flash memory structure comprises the steps of forming a protrusion in a semiconductor substrate, forming a plurality of storage structures at the sides of the protrusion, forming a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, forming a gate structure on the dielectric layer, and forming a plurality of diffusion regions at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate.
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