Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method
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United States of America Patent
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Issued Date -
Mar 4, 2010
app pub date -
Aug 29, 2008
filing date -
Aug 29, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method of manufacturing an integrated circuit provides a metrology mark (e.g., alignment mark or overlay mark). The method includes forming a first plurality of first structures arranged in a matrix in a substrate. Portions of the matrix are covered with a mask such that first portions of the matrix are left exposed and second portions of the matrix are covered. Signal response properties of exposed ones of the first structures in the matrix are altered to form a metrology mark. The metrology mark includes first and second mark portions with different signal response properties and which are aligned to a virtual grid. The evaluation of precisely positioned metrology marks may be improved with low impact on process complexity.
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