Memory Data Bus Placement and Control
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United States of America Patent
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Issued Date -
Mar 18, 2010
app pub date -
Sep 12, 2008
filing date -
Sep 12, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
In one embodiment, a memory device comprises a plurality of memory banks. At least two of the memory banks share the same bus. Logic is coupled to the memory banks via the different buses. The logic controls access to the memory banks. A bi-directional tri-state buffer is interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.
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