Interface between a verification environment and a hardware acceleration engine
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United States of America Patent
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Aug 6, 2013
Grant Date -
Apr 1, 2010
app pub date -
Sep 30, 2008
filing date -
Sep 30, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention allows a verification environment to be used to control and coordinate interaction with a design running on an accelerator or emulator without significant speed penalty. For example, an interface capable of communicating with test software running on an embedded processor is used to control and monitor the flow of data into the external interface of the design. Thus, a connection is made between the verification environment and the design under test running on the accelerator/emulator via a connection formed directly between the verification environment and embedded software running on the emulator for simulation and monitoring purpose at a very low frequency so that high-speed acceleration may still be achieved.
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