Disabling cache portions during low voltage operations

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United States of America Patent

PATENT NO 8103830
APP PUB NO 20100082905A1
SERIAL NO

12242321

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abella, Jaume Barcelona, ES 18 292
Casado, Javier Carretero Barcelona, ES 16 125
De, Vivek Beaverton, US 59 866
Gonzalez, Antonio Barcelona, ES 67 1831
Khellah, Muhammad M Tigard, US 115 1894
Monferrer, Pedro Chaparro Barcelona, ES 15 247
Vera, Xavier Barcelona, ES 34 389
Wilkerson, Christopher Portland, US 16 110
Zhang, Ming Portland, US 891 7236

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