Synchronization Controller For Multiple Multi-Threaded Processors
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United States of America Patent
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Issued Date -
May 20, 2010
app pub date -
Nov 17, 2008
filing date -
Nov 17, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A gated-storage system including multiple control interfaces, each control interface operatively connected externally to respective multithreaded processors. The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within any of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.
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