Importance

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Abstract

In one embodiment of the present invention, a shift register includes a plurality of stages which are activated in sequence. Each stage includes a logic circuit controlling first and second output circuits. The first output circuit includes a first switch in the form of a transistor, which connects an output of the stage to receive a pulse width control signal when the stage is active. A second switch in the form of a transistor connects the stage output to receive an inactive signal level when the stage is inactive. The second output circuit comprises a third switch in the form of a transistor, which connects a further output to receive an active signal level when the stage is active. A fourth switch in the form of a transistor connects the further output to receive an inactive signal level when the stage is inactive. The further output of each stage is connected to the logic circuit of at least one adjacent stage, such as a reset input of a preceding stage and/or a set input of a succeeding stage.

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First Claim