Hardware implementation of network testing and performance monitoring in a network device
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United States of America Patent
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Feb 1, 2011
Grant Date -
Jun 10, 2010
app pub date -
Jan 21, 2010
filing date -
Mar 22, 2006
priority date (Note) -
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Abstract
An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.
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