PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR
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United States of America Patent
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N/A
Issued Date -
Jun 24, 2010
app pub date -
Aug 1, 2006
filing date -
Aug 1, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A PLA contains an input plane (10) including a plurality of data lines (103) and a plurality of product term lines (104) having voltage levels changed in accordance with signal input to the plurality of data lines; and an output plane (20) including a plurality of product term lines (204) having voltage levels changed in accordance with the change of the voltage levels of the plurality of product term lines of the input plane and a plurality of data lines (203) for outputting signals in accordance with the voltage levels of the plurality of product term lines. In this PLA, at least one of the data lines of at least one of the input plane and the output plane has data terminals (101) at both ends thereof.
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