US Patent Application No: 2010/0156,488

Number of patents in Portfolio can not be more than 2000

DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
SAMSUNG ELECTRONICS CO., LTD.SUWON-SI GYEONGGI-DO54973

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hyun, Seok-hun Yongin-si, KR 10 30
Kim, Yang-ki Seoul, KR 13 101

Cited Art Landscape

Patent Info (Count) # Cites Year
 
POLARIS INNOVATIONS LIMITED (1)
* 2009/0267,663 ELECTRONIC SYSTEM THAT ADJUSTS DLL LOCK STATE ACQUISITION TIME 5 2008
 
NANYA TECHNOLOGY CORPORATION (1)
* 2008/0169,851 DELAY LOCKED LOOP 2 2007
 
SAMSUNG ELECTRONICS CO., LTD. (2)
* 7,786,752 Memory systems, on-die termination (ODT) circuits, and method of ODT control 10 2007
* 2010/0213,992 Delay locked loop circuit and operation method thereof 5 2010
 
TEXAS INSTRUMENTS INCORPORATED (1)
* 2009/0033,388 Systems and Methods for Reduced Area Delay Locked Loop 3 2007
 
HYNIX SEMICONDUCTOR INC. (1)
* 2011/0058,433 LATENCY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING LATENCY 2 2009
 
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. (1)
* 7,551,012 Phase shifting in DLL/PLL 3 2007
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
* 2011/0221,496 DLL CIRCUIT 2 2011
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
* 8,400,845 Column address strobe write latency (CWL) calibration in a memory system 0 2011
* 2012/0176,850 COLUMN ADDRESS STROBE WRITE LATENCY (CWL) CALIBRATION IN A MEMORY SYSTEM 1 2011
 
U.S. BANK NATIONAL ASSOCIATION (1)
* 2015/0028,928 PHASE INTERPOLATORS AND PUSH-PULL BUFFERS 3 2014
 
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (1)
9,300,304 Self-biased delay locked loop with delay linearization 0 2012
 
PS4 LUXCO S.A.R.L. (2)
* 7,932,759 DLL circuit and control method therefor 2 2009
* 2010/0060,334 DLL CIRCUIT AND CONTROL METHOD THEREFOR 8 2009
 
Micron Technology, Inc. (3)
8,643,418 Apparatus and methods for altering the timing of a clock signal 1 2011
9,225,319 Apparatus and methods for altering the timing of a clock signal 0 2014
9,275,698 Memory system and method using stacked memory device dice, and system using the memory system 0 2014
 
NATIONAL CHUNG CHENG UNIVERSITY (2)
* 8,294,498 Clock de-skewing delay locked loop circuit 0 2011
* 2012/0112,810 CLOCK DE-SKEWING DELAY LOCKED LOOP CIRCUIT 2 2011
 
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY (2)
* 8,049,543 Delay locked loop, electronic device including the same, and method of operating the same 6 2009
* 2010/0194,456 Delay locked loop, electronic device including the same, and method of operating the same 3 2009
 
HYNIX SEMICONDUCTOR INC. (7)
* 7,932,758 Delay locked loop circuit and operation method thereof 0 2009
* 2010/0141,312 DELAY LOCKED LOOP CIRCUIT AND OPERATION MEHTOD THEREOF 1 2009
* 7,969,213 DLL circuit 2 2009
* 2010/0156,487 DLL CIRCUIT 1 2009
* 8,610,475 Integrated circuit 0 2010
* 2012/0105,119 INTEGRATED CIRCUIT 2 2010
* 8,106,694 DLL circuit 2 2011
 
SUNPLUS TECHNOLOGY CO., LTD. (2)
* 8,076,962 Frequency synthesis system with self-calibrated loop stability and bandwidth 4 2010
* 2011/0063,004 Frequency synthesis system with self-calibrated loop stability and bandwidth 4 2010
* Cited By Examiner