Importance

Loading Importance Indicators...

Abstract

An integrated circuit with an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. A set of logical channels are associated with a logical mux channel. The nodes are adapted to carry out operations utilizing a given logical mux channel associated therewith in order to identify a logical channel that is associated with the given logical mux channel and that has a predetermined ready state. In the preferred embodiment, the operations are invoked by a calling thread that is blocked in the event that no logical channel associated with the given logical mux channel has a predetermined ready state. The calling thread is then reactivated in the event that at least one logical channel associated with the given logical mux channel transitions to the predetermined ready state. Preferably, the nodes include a recirculation queue and logic that stores event messages in the recirculation queue. Each given event message provides an indication that an identified logical channel associated with an identified logical mux channel has transitioned to the predetermined ready state. The logic processes the recirculation queue to reactivate calling threads in accordance with the event messages stored therein. The operations temporarily remove the identified logical channel from the given logical mux channel such that the identified local channel behaves like an independent logic channel. The operations that identify the logical channel associated with the given logical mux channel are fair between all logical channels that are associated with the given logical mux channel.

Loading the Abstract Image...

First Claim