Non-volatile memory and method with write cache partition management methods

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United States of America Patent

PATENT NO 8244960
APP PUB NO 20100174847A1
SERIAL NO

12348899

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Abstract

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A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.

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Patent Owner(s)

  • SANDISK TECHNOLOGIES LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bennett, Alan David Edinburgh, GB 48 3513
Gorobets, Sergey Anatolievich Edinburgh, GB 175 9352
Paley, Alexander Kfar-Saba, IL 24 761
So, Bum Suck San Jose, US 8 721
Tomlin, Andrew San Jose, US 30 1504
Traister, Shai San Jose, US 36 1547
Wu, William S Cupertino, US 25 1122
Zilberman, Eugene Richmond Hill, CA 13 1249

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