Flash memory and method for a cache portion storing less bit per cell than a main portion
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United States of America Patent
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Mar 27, 2012
Grant Date -
Aug 12, 2010
app pub date -
Apr 26, 2010
filing date -
Jun 6, 2006
priority date (Note) -
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Abstract
A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.
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