Dual Interconnection in Stacked Memory and Controller Module

United States of America Patent

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Issued Date
Oct 28, 2010
app pub date
Apr 28, 2009
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Apr 28, 2009

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Abandoned

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Abstract

A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

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Patent Owner(s)

Patent Owner	Address
WAFER-LEVEL PACKAGING PORTFOLIO LLC	20400 STEVENS CREEK BLVD CUPERTINO CA 95014

International Classification(s)

H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Marcoux, Phil P	Mountain View, US	12	384

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Dual Interconnection in Stacked Memory and Controller Module

Number of patents in Portfolio can not be more than 2000

United States of America Patent

12431569

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12431569

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