Threshold voltage improvement employing fluorine implantation and adjustment oxide layer

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United States of America Patent

PATENT NO 7893502
APP PUB NO 20100289088A1
SERIAL NO

12465908

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Abstract

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An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

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Patent Owner(s)

Patent OwnerAddress
INFINEON TECHNOLOGIES AG85579 NEUBIBERG

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Han, Jin-Ping Fishkill, US 53 600
Lee, Yong Meng Beacon, US 49 431
Li, Weipeng Beacon, US 18 179
Park, Dae-Gyu Poughquaq, US 96 3651
Sherony, Melanie J Fishkill, US 13 111

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