Importance

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Abstract

An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.

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First Claim