
US Patent Application No: 2010/0303,157
Number of patents in Portfolio can not be more than 2000
SEMICONDUCTOR INTEGRATED CIRCUIT
Stats
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Dec 2, 2010
Publication date -
May 19, 2010
filing date -
12/783,320
serial no -
Granted
status
Importance
Abstract
The present invention is directed to lessen burden at the time of solving a conflict of overlapping processes in processes for a plurality of interruption factors. On completion of data transfer to an external memory, a data transfer completion interruption of high priority is generated. In the case where data transfer of predetermined number of packets is not completed in reception interruption, a timer interruption of low priority is generated. Before processing data in an external memory responding to the interruption, the number of transfer packets is obtained from a counter. After restart of reception, the counter stores the number of transfer restart packets. After obtaining the number of transfer packets from a counter responding to the occurrence of the timer interruption, a data transfer completion interruption is generated. According to the obtained number of transfer packets, execution of either a process responding to occurrence of the timer interruption or a process responding to occurrence of the data transfer completion interruption is omitted.
First Claim
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