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Abstract

The present specification discloses a processing architecture that has multiple levels of parallelism and is highly configurable, yet optimized for media processing. At the highest level, the architecture is structured to enable each processor, which is dedicated to a specific media processing function, to operate substantially in parallel. In addition to processor-level parallelism, each processing unit can operate on multiple words in parallel, rather than just a single word per clock cycle. Moreover, at the instruction level, the control data memory, data memory, and function specific dath paths can be controlled all within the same clock cycle. Additionally, the processor has multiple layers of configurability, with the extendable data path of the processor being capable of being configured to perform specific processing functions, such as entropy encoding, discrete cosine transform (DCT), inverse discrete cosine transform (IDCT), motion compensation, motion estimation, de-blocking filter, de-interlacing, de-noising, quantization, and dequantization.

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First Claim