ANTICOUNTERFEITING SYSTEM AND METHOD FOR INTEGRATED CIRCUITS
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United States of America Patent
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Issued Date -
Mar 3, 2011
app pub date -
Sep 3, 2010
filing date -
Sep 3, 2009
priority date (Note) -
Abandoned
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Abstract
An integrated circuit die comprises a device layer comprising a plurality of semiconductor devices; an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.
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