Interfaces, circuits, and methods for communicating with a double data rate memory device
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United States of America Patent
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Jul 31, 2012
Grant Date -
Mar 17, 2011
app pub date -
Sep 11, 2009
filing date -
Sep 11, 2009
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Abstract
An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.
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- 15 United States
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Patent Owner(s)
- AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;AVAGO TECHNOLOGIES ENTERPRISE IP PTE. LTD.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Evans, Scott T | Fort Collins, US | 14 | 143 |
Haugestuen, Benjamin P | Fort Collins, US | 2 | 57 |
Linam, David | Fort Collins, US | 4 | 58 |
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