STRUCTURE AND METHOD FOR SEMICONDUCTOR TESTING

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United States of America Patent

APP PUB NO 20110074459A1
SERIAL NO

12887491

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An embodiment of a test structure in accordance with the present invention comprises a pair of interdigitated comb portions of a metallization layer present in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element. A third portion of the metallization layer comprises a serpentine metal line interposed between the comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (V.sub.bd) and time dependent dielectric breakdown (TDDB) of the ILD; (4) contamination in the metallization portions with mobile ions; and (5) k valve and drift in k value of the ILD. A bias voltage may be applied to the polysilicon heater to accomplish temperature control during testing.

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Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION18 ZHANGJIANG ROAD PUDONG NEW AREA SHANGHAI 201203
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONNO 18 WEN CHANG RD ECONOMIC-TECHNOLOGICAL DEVELOPMENT AREA DAXING DISTRICT BEIJING 100716

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gong, Bin Shanghai, CN 14 39
Ruan, Wei Wei Shanghai, CN 4 20
Shi, Wen Shanghai, CN 63 225

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