LOW POWER PROGRAMMABLE LOGIC DEVICES
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United States of America Patent
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Issued Date -
Mar 31, 2011
app pub date -
Sep 25, 2009
filing date -
Sep 25, 2009
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Circuits and power up sequences to reduce power consumption in programmable logic devices is disclosed. A multiplexer (MUX) for a programmable logic device comprising: a plurality of inputs and an output; and a configuration circuit comprising a plurality of memory elements, each memory element generating a control signal, the configuration circuit comprising a first mode of operation to force each of said control signals to a first voltage level regardless of the memory state in the memory element; and a first device coupling a power supply voltage to the output, said first device having a gate electrode controlled by a said control signal of the configuration circuit; and one or more second devices coupling one or more inputs to the output, each said second device having a gate electrode controlled by a said control signal of the configuration circuit; wherein, the first device is in a conducting state to couple the power supply voltage to the MUX output during the first mode of operation of the configuration circuit.
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