Operating point management in multi-core architectures

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United States of America Patent

PATENT NO 9619009
SERIAL NO

12980532

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Abstract

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For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. Other embodiments are also disclosed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lamdan, Oren Kiryat Tivon, IL 20 600
Naveh, Alon Ramat Hasharon, IL 105 2715
Rotem, Efraim Haifa, IL 194 3407

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